do you have any plans to support verilator in future? I think there are a lot of open source enthusiasts (including me) which do not have access to expensive tooling. In this video you will learn How to setup Native link for Simulation using Altera Quartus II toolThe tools used in this video are Quartus II 14.1 and Modelsi. A lot of the IPs cause compilation errors. My goal is to get pulpissimo working with the verilator compiler which is painful as verilator is very pedantic. I wonder if anyone has experienced similar with the Altera/Intel Modelsim FPGA Edition or Modelsim DE or even QuestaSim respectively. So I do not trust the Modelsim Altera Starter / Ubuntu 16.04 flow. It might be the case that there are similar issues with other IPs also.
Modelsim altera path driver#
C:\intelFPGAlite\16.1) authorize USB JTAG Blaster II driver installation Run the Quartus Prime 16.
Modelsim altera path install#
run QuartusLiteSetup-16.1.0.196-windows, install to a path without spaces in the name (e.g. Both are dirty hacks I would not suggest to introduce. include device support for Cyclone IV and ModelSim-Altera Starter Edition. Also working around the generate statement up in the hierarchy in hwpe_stream_sink.sv fixes the issue. Forcing this parameter with the deprecated defparam syntax fixes the issue. This seems to be a Modelsim issue as the code looks straight forward to me.
For whatever reason the parameter assignment of 68 Bit does not propagate down the hierachy and the actual instance i_fifo in file hwpe_stream_tcdm_fifo_store.sv is falling back to the parameter default which is 32 Bit. 1,308 Activity points 2,231 The Altera Modelsim Starter Edition is free. Unfortunately the accelerator/hwme example fails! I nailed down the root cause to an incorrect bit with of the hwpe_stream_fifo. verilog-tool uses a Makefile if one exists in the current directory. Actually, it is not useable for designs as complex as pulpissimo. That is why simulation performance is extremely low. no vopt, 10.000 lines of code, 3.000 instances, 32 Bit only. Modelsim Altera Starter is limited in features e.g. After that I successfully run the Hello World example for both the pulpissimo and the pulp platform. Finally I had to hack the plp_rtl_runner.py in the SDK because Altera Starter is available as 32 Bit version only. Additionally to the libraries to be added, the top-level testbench has to be changed from vopt_tb to tb_pulp in run.tcl. To get it working I had to hack the flow as explained. There are some workarounds required as Ubuntu is not supported officially. Hi I managed to get pulpissimo running with Altera/Intel Modelsim 10.6c Starter on Ubuntu 16.04.
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